Program Block Vs Module In System Verilog

Module Instantiation: Refer to modules instantiated in other modules. Program 1 shows examples of input/output ports for a simple module instantiation. Module Declaration: Refer to the actual Verilog code written for a module. Program 2 shows examples of inputs/outputs within a module declaration. Notice that each input and output. Verilog is based on module level testbench. SystemVerilog is based on class level testbench. It is standardized as IEEE 1364. It is standardized as IEEE 1800-2012. Verilog is influenced by C language and Fortran programming language. SystemVerilog is based on Verilog, VHDL and c programming language. It has file extension.v or.vh. There are two types of procedural assignments called blocking and non-blocking. Blocking assignment, as the name says, gets executed in the order statements are specified. The “=” is the symbol used for blocking assignment representation. Non-blocking assignment allows scheduling of assignments. It will not block the execution.

Systemverilog Module
Define In Systemverilog
Systemc Vs Systemverilog

RAM Verilog Code | ROM Verilog Code

This page covers RAM verilog code and ROM verilog code.It also provides link which compares RAM vs ROM.

Systemverilog Module

RAM Verilog code

Following is the figure and verilog code of RAM (Random Access Memory).

module RAM_code(out, in, addr, RW, CS);
output [7:0] out;
input [7:0] in;
input [3:0] addr;
input RW, CS;
reg [7:0] out;
reg [7:0] DATA[15:0];
always @(negedge CS)
begin
if(RW1'b0) //READ
out=DATA[addr];
else
if(RW1'b1) //WRITE
DATA[addr]=in;
else
out=8'bz;
end
endmodule

ROM Verilog code

Following is the figure and verilog code of ROM (Read Only Memory).

module ROM_code(out, addr, CS);
output[15:0] out;
input[3:0] addr;
input CS;
reg [15:0] out;
reg [15:0] ROM[15:0];
always @(negedge CS)
begin
ROM[0]=16'h5601; ROM[1]=16'h3401;
ROM[2]=16'h1801; ROM[3]=16'h0ac1;
ROM[4]=16'h0521; ROM[5]=16'h0221;
ROM[6]=16'h5601; ROM[7]=16'h5401;
ROM[8]=16'h4801; ROM[9]=16'h3801;
ROM[10]=16'h3001; ROM[11]=16'h2401;
ROM[12]=16'h1c01; ROM[13]=16'h1601;
ROM[14]=16'h5601; ROM[15]=16'h5401;
out=ROM[addr];
end
endmodule

Program Block Vs Module In System Verilog

Comparison between RAM and ROM

MRAM vs SRAM vs DRAM
RAM vs ROM

Define In Systemverilog

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1. Verilog :
Verilog is a Hardware Description Language (HDL). It is a computer language which is used to describe the structure and behavior of electronic circuits. In 1983 Verilog language started as a proprietary language for hardware modelling at Gateway Design Automation Inc and later it became IEEE standard 1364 in 1995 and started becoming more widely used. Verilog is based on module level testbench.

2. SystemVerilog :
SystemVerilog is a combination of both Hardware Description Language (HDL) and Hardware Verification Language (HVL) and combined termed as HDVL. Means it describe the structure and behavior of electronic circuits as well as it verifies the electronic circuits written in a Hardware Description Language. SystemVerilog acts as a superset of Verilog with a lot extensions to Verilog language in 2005 and became IEEE standard 1800 and again updated in 2012 as IEEE 1800-2012 standard. SystemVerilog is based on class level testbench which is more dynamic in nature.

Difference between Verilog and SystemVerilog :

S.No.	VERILOG	SYSTEMVERILOG
01.	Verilog is a Hardware Description Language (HDL).	SystemVerilog is a combination of both Hardware Description Language (HDL) and Hardware Verification Language (HVL).
02.	Verilog language is used to structure and model electronic systems.	SystemVerilog language is used to model, design, simulate, test and implement electronic system.
03.	It supports structured paradigm.	It supports structured and object oriented paradigm.
04.	Verilog is based on module level testbench.	SystemVerilog is based on class level testbench.
05.	It is standardized as IEEE 1364.	It is standardized as IEEE 1800-2012.
06.	Verilog is influenced by C language and Fortran programming language.	SystemVerilog is based on Verilog, VHDL and c++ programming language.
07.	It has file extension .v or .vh	It has file extension .sv or .svh
08.	It supports Wire and Reg datatype.	It supports various datatypes like enum, union, struct, string, class.
09.	It is based on hierarchy of modules.	It is based on classes.
10.	It was began in 1983 as proprietary language for hardware modelling.	It was originally intended as an extension to Verilog in the year 2005.

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